The present invention relates generally to semiconductor devices, and more specifically, to constructing multiple dielectrics for gate-all-around transistors.
In nanometer scale devices, gate structures are often disposed between fin structures or other conducting structures, such as nanosheets. In many instances, the conducting or semiconducting structures are formed closer together due to scaling with smaller node technology sizes. This can be a limiting factor in the reduction of device size scaling. While fin field effect transistors (finFETs) and/or nanosheets can benefit from tight device-device spacing, these dimensions can limit device scaling. Further, devices needing a thicker dielectric for higher voltage operation are even more limited in the allowable dimensions. Higher voltage devices for input and/or output circuits need thicker gate dielectrics as compared to standard gate devices, which have a lower voltage and can be employed, e.g., in logic devices.